To reduce the cost and increase the performance or electronic computers, it is desirable to place as many electronic circuits in as small a region as possible in order to reduce the distance over which electrical signals must travel from one circuit to another. This can be achieved by fabricating, on a given area of a semiconductor chip, as many electronic circuits as feasible within a given fabrication technology. These dense chips are generally disposed on the surface of a substrate in a side by side arrangement with space left therebetween to provide regions for electrical conductors for electrical interconnection of the chips. The chip contact locations can be electrically interconnected to substrate contact locations by means of wires bonded in between the chip contact location and substrate contact locations. Alternatively, a TAB tape (which is a flexible dielectric layer having a plurality of conductors disposed thereon) can be used for this electrical interconnection. Alternatively, the semiconductor chips may be mounted in a flip-chip configuration wherein an array of contact locations on the semiconductor chip is aligned with and electrically interconnected to an array of contact locations on a substrate by means of solder mounds disposed between corresponding chips and substrate contact locations. This side by side arrangement of electronic devices is not the most dense configuration which can be achieved.
In the microelectronics industry, integrated circuits, such as semiconductor chips, are mounted onto packaging substrates to form modules. In high performance computer applications, the modules contain a plurality of integrated circuits. A plurality of modules are mounted onto a second level of packages such as a printed circuit board or card. The cards are inserted into a frame to form a computer.
For nearly all convention interconnection package, except for double sided cards, signals from one chip on the package travel in a two dimensional wiring net to the edge of the package then travel across the card or board or even travel along cables before they reach the next package which contain the destination integrated circuit chip. Therefore, signals must travel off of one module onto wiring on a board or onto wiring on a cable to a second module and from a second module to the destination integrated circuit chip in the second module. This results in a long package time delay and increases the demands on wireability of the two dimensional wiring arrays.
As the performance requirements of a mainframe computer continue to increase, the signal propagation time for communications from module to module, chip to chip and even device to device become critical. The current solution to this problem is to place the chips as close together as possible on a planar substrate and combine as many circuits as possible onto the substrate using insulators having dielectric constants as low as possible between wiring layers.
However, it is becoming apparent that such solutions will not allow future generation machines to reach the desired performance levels. One of the most significant factor is the time required for a signal to cross the length of a module. Three dimensional packaging structures will overcome the problem of the signal propagation distances in the planar packages, but the difficulty has been finding a suitable way to interconnect the devices in such a structure.
An improvement in chip interconnection propagation time and an increase in real chip packaging density can be achieved if three dimensional wiring between closely spaced planes of chips can be achieved.